| 摘要 |
<p>Disclosed is a shift register (200, 400) comprising an input (205), an output (230) and a plurality of register cells (210) serially connected between the input and the output, each register cell being connected to a neighboring cell via a node, wherein at least some of said nodes comprise a multiplexer (220) having an output coupled to the downstream register cell and a plurality of inputs, each of said plurality of inputs being coupled to a different upstream register cell such that different length sections of the shift register can be selectively bypassed, the shift register further comprising a set of parallel lO channels (230, 410) facilitating conversion between interleaved and de-interleaved data, each of said channels being coupled to a different one of said nodes, the number of parallel lO channels being smaller than the total number of register cells in the shift register.</p> |
