发明名称 DYNAMIC REAL-TIME DELAY CHARACTERIZATION AND CONFIGURATION
摘要 <p>In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.</p>
申请公布号 EP2329497(A4) 申请公布日期 2015.12.23
申请号 EP20090813552 申请日期 2009.09.09
申请人 ALTERA CORPORATION 发明人 TAN, JUN PIN;KOAY, WEI YEE;ANG, BOON JIN;WONG, CHOONG KIT;SOH, GUANG SHENG
分类号 G11C7/22;G11C8/00;G11C29/02;H03K5/13;H03K19/173;H03L7/00 主分类号 G11C7/22
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