发明名称 |
DATA PROCESSING METHOD, PRECODING METHOD, AND COMMUNICATION DEVICE |
摘要 |
An encoder outputs a first bit sequence having N bits. A mapper generates a first complex signal s 1 and a second complex signal s2 with use of bit sequence having X+Y bits included in an input second bit sequence, where X indicates the number of bits used to generate the first complex signal s1, and Y indicates the number of bits used to generate the second complex signal s2. A bit length adjuster is provided after the encoder, and performs bit length adjustment on the first bit sequence such that the second bit sequence has a bit length that is a multiple of X+Y, and outputs the first bit sequence after the bit length adjustment as the second bit sequence. As a result, a problem between a codeword length of a block code and the number of bits necessary to perform mapping by a set of modulation schemes is solved. |
申请公布号 |
EP2945291(A4) |
申请公布日期 |
2015.12.23 |
申请号 |
EP20130870553 |
申请日期 |
2013.12.27 |
申请人 |
PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA |
发明人 |
MURAKAMI, YUTAKA;KIMURA, TOMOHIRO;OUCHI, MIKIHIRO |
分类号 |
H03M13/19;H03M13/27;H04B7/06;H04J99/00;H04L1/00;H04L1/08 |
主分类号 |
H03M13/19 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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