Read assist techniques in a memory device

摘要

A memory device and method of operation, comprising an array of bitcells (32, figure 2), such as an SRAM bitcell (figure 1), each bitcell selectively coupled to one out of a plurality of wordlines WL0-WLn (34 figure 2). Access to a selected array bitcell requires an asserted voltage on a selected wordline associated with the bitcell. In addition, a read assist circuit is provided and configured such that when read access to the selected bitcell is executed, a reduction in the asserted voltage on the selected wordline ((see figure 7) is implemented by selective connection 52, of the selected wordline to one or more than one additional wordlines. Selective connection of the appropriate wordlines is implemented in one embodiment (figures 4A-5) by means of PMOS MOSFET devices 52 having a relatively narrow width (0.75u) thus having a modest on resistance. All other wordline drivers to non activated wordlines are tied to ground potential by stronger NMOS devices (5.1 um NMOSFets) having lower on resistances. The selected wordline driver provides a positive potential on the wordline via a strong pull up PMOS device of width 9um in the embodiment. Thus a potential divider (resistive tap) network is provided (Figure 4B) by the read assist circuit thus reducing or dropping the asserted voltage of the specific wordline during the first period of reading (figure 7). A read assist enable signal line is held low during read assist, and is connected to the gate of the PMOSFet transistors which couple adjacent wordlines together. The arrangement and number of connected wordlines via PMOSFet devices may vary (figures 4, 5, and 6). The timing of the read assist operation is such that following expiry, the affected wordline resumes a full supply potential as a result of the read assist enable line set to a high potential (figure 9). The read assist circuit has a highly efficient physical layout implementation (figures 10 and 11). A cell library can also be stored on a computer readable storage medium. Stability, access disturbance margins (ADM) and static noise margins (SDM) are all improved by the read assist circuit and method.