Method and apparatus for distributed generation of multiple configurable ratioed clock domains within a high speed domain

摘要

Implementations of the present disclosure involve an apparatus and/or method for providing one or more clock signals within a processing device. In particular, one or more counter devices may be integrated into a microprocessor design that operates on a system clock signal to provide ratioed synchronous clock signals for use by the microprocessor. Additionally, one or more synchronization pulse signals are also generated from the one or more counter devices to facilitate communication between domains of the microprocessor that may operate on separate clock frequencies. Such synchronization pulse signals may also provide for a virtual clock signal within a clock domain to create a low frequency logic cluster within a high frequency domain of the microprocessor. A synchronous, low frequency reset signal is also disclosed to synchronize the counting devices to the system clock without the need for an additional high frequency signal path in the microprocessor design.

主权项

1. A microprocessor comprising: a processor clock generating circuit configured to generate a processor clock signal, the processor clock generating circuit comprising a plurality of clock signal generating circuits each configured to provide a repeating clock signal and a clock multiplexer configured to output one of the plurality of repeating clock signals based on a first value on a clock selection input; and
a plurality of logic domains, wherein each of the plurality of logic domains comprises a header portion comprising at least one counter configured to generate an output value signal that increments or decrements on each cycle of the processor clock signal; wherein each header portion is configured to generate a plurality of clock signals from the output signal of the at least one counter of each header portion, the plurality of clock signals being synchronized and ratioed to the processor clock signal; and a reset control unit configured to provide a reset signal to the at least one counter of each of the plurality of logic domains, the reset signal configured to reset the output value signal of the at least one counter of each of the plurality of logic domains to a beginning value when the reset signal is asserted; wherein the reset signal is transmitted to the at least one counter of each of the plurality of logic domains at a lower frequency than the frequency of the processor clock signal; wherein each header portion is further configured to generate one or more synchronization pulse signals configured to enable communication between portions of the microprocessor, the synchronization pulse signals being synchronized to the processor clock signal.