Trace controller for processor, periphery, address, control, and data lines

摘要

An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

主权项

1. A system comprising:
address lines, control lines, and data lines; processor circuitry coupled to the address lines, the control lines, and the data lines; peripheral circuitry coupled to the address lines, the control lines, and the data lines; and trace domain circuitry coupled to the address lines, the control lines, and the data lines, the trace domain circuitry including:
trace controller circuitry having inputs coupled to the address lines, the control lines, and the data lines, having external control inputs and an external data output, and having internal control inputs and outputs;multiplexer circuitry having inputs coupled with the address lines and the data lines, a control input coupled with one of the internal control outputs of the trace controller circuitry, and an output;trace memory circuitry having a data input coupled with the output of the multiplexer circuitry, control inputs and outputs coupled with the internal control inputs and outputs of the trace controller circuitry, and a data output;output circuitry having a data input coupled with the data output of the trace memory circuitry, control inputs and outputs coupled with the internal control inputs and outputs of the trace controller circuitry, and a data output; andbuffer circuitry having a data input coupled with the data output of the output circuitry, a control input coupled with one of the internal control outputs of the trace controller circuitry, and an external trace data output.