Wafer-level package device having high-standoff peripheral solder bumps

摘要

A wafer-level package device and techniques for fabricating the device are described that include a second integrated circuit chip electrically coupled to a base integrated circuit chip, where the second integrated circuit chip is placed on and connected to the base integrated circuit chip between multiple high-standoff peripheral pillars with solder bumps. In implementations, the wafer-level package device that employs example techniques in accordance with the present disclosure includes a base integrated circuit chip, multiple high-standoff peripheral pillars with solder bumps, and a second integrated circuit chip electrically coupled to the base integrated circuit chip and placed on the base integrated circuit chip in the center of an array of high-standoff peripheral pillars with solder bumps.

主权项

1. A wafer-level package device comprising:
a base integrated circuit chip including an integrated circuit; at least one pillar formed on a first side of the base integrated circuit chip device, where the at least one pillar has a high standoff peripheral arrangement and includes at least one solder bump formed on the pillar; and a second integrated circuit chip device electrically coupled to the first side of the base integrated circuit chip device, the second integrated circuit chip device disposed in a center of the at least one pillar with the high standoff peripheral arrangement, where the second integrated circuit chip device includes at least one solder bump formed on a side distal from the first side of the base integrated circuit chip.