发明名称 Via pre-fill on back-end-of-the-line interconnect layer
摘要 The present disclosure relates to a metal interconnect layer formed using a pre-fill process to reduce voids, and an associated method. In some embodiments, the metal interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.
申请公布号 US9219033(B2) 申请公布日期 2015.12.22
申请号 US201414221509 申请日期 2014.03.21
申请人 Taiwan Semiconductor Manufacturing Co., Ltd. 发明人 Peng Chao-Hsien;Kuo Chi-Liang;Lee Ming-Han;Lee Hsiang-Huan;Shue Shau-Lin
分类号 H01L23/522;H01L21/00;H01L23/528;H01L23/532;H01L21/768;H01L21/285;H01L21/288 主分类号 H01L23/522
代理机构 Eschweiler & Associates, LLC 代理人 Eschweiler & Associates, LLC
主权项 1. A conductive interconnection layer comprising: a dielectric layer disposed over a substrate; an opening extending downwardly through the dielectric layer comprising an upper portion above a horizontal plane and a lower portion below the horizontal plane; a first conductive layer filling the lower portion of the opening; an upper barrier layer disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening; a second conductive layer disposed over the upper barrier layer filling the upper portion of the opening; and a metal oxide barrier layer abutting the upper barrier layer and continuously extending around top, bottom and sidewall regions of the first conductive layer.
地址 Hsin-Chu TW