System cache with coarse grain power management

摘要

Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and individual ways are powered down when cache activity is low. A maximum active way configuration register is set by software and determines the maximum number of ways which are permitted to be active. When searching for a cache line replacement candidate, a linear feedback shift register (LFSR) is used to select from the active ways. This ensures that each active way has an equal chance of getting picked for finding a replacement candidate when one or more of the ways are inactive.

主权项

1. A cache comprising:
a cache memory arranged as a set associative memory having a plurality of ways; a configuration register comprising a first field and a second field, wherein the first field indicates whether an exact number of ways is specified or a maximum number of ways is specified by the second field, and wherein the second field specifies a number of ways; and a cache control unit coupled to the cache memory and the configuration register,
wherein the cache control unit is configured to:manage power to the plurality of ways by dynamically enabling and disabling ways of the plurality of ways; andlimit a number of active ways to the maximum number specified by the configuration register; wherein when the first field indicates an exact number of ways, a number of active ways in the cache memory is fixed at a number of ways specified by the second field; and wherein when the first field indicates a maximum number of ways, a number of active ways in the cache memory is permitted to vary up to a number of ways specified by the second number.