| 发明名称 | Memory structure and preparation method thereof | ||
| 摘要 | A memory structure includes a control unit and a memory unit electrically connected to the control unit. The control unit includes a source and a drain; an active layer in contact with a portion of the source and a portion of the drain; a gate layer; and a gate insulation layer disposed between the active layer and the gate layer. The memory unit includes a bottom electrode layer; a top electrode layer; and a resistive switching layer interposed between the bottom electrode layer and the top electrode layer, which the resistive switching layer and the active layer are formed of aluminum zinc tin oxide (AZTO). | ||
| 申请公布号 | US9219099(B1) | 申请公布日期 | 2015.12.22 |
| 申请号 | US201414561194 | 申请日期 | 2014.12.04 |
| 申请人 | NATIONAL CHIAO TUNG UNIVERSITY | 发明人 | Liu Po-Tsun;Fan Yang-Shun;Chen Chun-Ching |
| 分类号 | H01L29/02;H01L27/24;H01L45/00 | 主分类号 | H01L29/02 |
| 代理机构 | CKC & Partners Co., Ltd. | 代理人 | CKC & Partners Co., Ltd. |
| 主权项 | 1. A memory structure, comprising: a control unit, comprising: a source and a drain;an active layer in contact with a portion of the source and a portion of the drain;a gate layer; anda gate insulation layer disposed between the active layer and the gate layer; and a memory unit electrically connected to the control unit, the memory unit comprising: a bottom electrode layer;a top electrode layer; anda resistive switching layer interposed between the bottom electrode layer and the top electrode layer, wherein the resistive switching layer and the active layer are formed of aluminum zinc tin oxide (AZTO). | ||
| 地址 | Hsinchu TW | ||