Decision feedback equalization slicer with enhanced latch sensitivity

摘要

A decision feedback equalization slicer for ultra-high-speed backplane Serializer/Deserializer (SerDes) with improved latch sensitivity. A first regeneration stage can be configured in association with a second regeneration stage to compensate for channel impairment such as Inter-symbol interference due to channel loss, reflections due to impedance mismatch, and cross-talk interference from neighboring electrical channels. The first regeneration stage includes two first stage slicers corresponding to a set of speculative decision (+h1 and −h1). A multiplexer can be placed at an input port of the second regeneration stage to select the set of speculative decision based on previous decision in order to save hardware and power. The DFE slicer samples the Input signal, regenerates the sampled data, stores the data on storage element like RS-latch or flip-flop, and presets the regeneration nodes to high or low values in preparation for sampling the next input data.

主权项

1. A decision feedback equalization circuit, comprising:
a first regeneration stage in association with a second regeneration stage to compensate for interference, wherein said first regeneration stage comprises at least two slicers corresponding to a set of speculative decisions; a multiplexer placed at an input port of said second regeneration stage to select a set of speculative decisions based on a previous decision; a precise clock generation circuit connected to said first regeneration stage and said second regeneration stage to maximize re-generation time and improve sensitivity; and a differential-pair that is re-usable for offset cancellation by merging an offset correction signal with a speculative h-tap correction signal to cancel a large offset without adding an additional load to said circuit.