发明名称 |
GaN epitaxial growth method |
摘要 |
By using a nano-scale patterning process, a dislocation defect density of a GaN epitaxy layer can be further reduced. This is because the nano-scale epitaxy structure dimension is advantageous to the reduction of the strain energy accumulated by mismatched lattices, thereby decreasing the possibility of generating defects. It is verified that the nano-scale patterning process can effectively decrease the dislocation defect density of the GaN epitaxial layer on a sapphire substrate. Considering uniformity and reproducibility on the application of the large-size wafer, the invention has utilized the soft mask NIL patterning technology to successfully implement the uniform deposition and position control of the InAs quantum dot on a GaAs substrate. This further utilizes the NIL technology in conjunction with dry-etching to perform the nano-scale patterning on a heterogeneous substrate, such as Si, sapphire or the like. |
申请公布号 |
US9218965(B2) |
申请公布日期 |
2015.12.22 |
申请号 |
US201414229285 |
申请日期 |
2014.03.28 |
申请人 |
NATIONAL TSING HUA UNIVERSITY |
发明人 |
Cheng Keh-Yung;Wang Yu-Li;Yang Wei-Chen;Chiu Shao-Yen |
分类号 |
H01L21/00;H01L21/02;H01L21/306;H01L21/3065 |
主分类号 |
H01L21/00 |
代理机构 |
Muncy, Geissler, Olds & Lowe, P.C. |
代理人 |
Muncy, Geissler, Olds & Lowe, P.C. |
主权项 |
1. A gallium nitride epitaxial growth method, comprising the steps of:
(1) providing a semiconductor laminated layer or a heterogeneous substrate; (2) forming a platform on the semiconductor laminated layer or the heterogeneous substrate to serve as a use of a flexible nano-imprint; (3) forming a nano-pillar or a nano-hole on the semiconductor laminated layer or the heterogeneous substrate; and (4) forming a heterogeneous epitaxy region on the semiconductor laminated layer or the heterogeneous substrate; wherein the step (3) of forming the nano-pillar or the nano-hole comprises: (i) using the flexible nano-imprint with a predetermined period on the semiconductor laminated layer or the heterogeneous substrate; (ii) performing a dry-etching process once on the semiconductor laminated layer or the heterogeneous substrate to transfer print a nano-pattern; and (iii) performing a peel off process so that the nano-pattern forms the nano-pillar or the nano-hole on the semiconductor laminated layer or the heterogeneous substrate. |
地址 |
Hsinchu TW |