发明名称 Nonvolatile semiconductor memory device capable of improving retention/disturb characteristics of memory cells and method of operating the same
摘要 A semiconductor memory device includes a memory cell array configured to store data; peripheral circuits configured to perform program verifying operation, read operation, and erase verifying operation on the memory cell array; and a control circuit configured to control the peripheral circuits, wherein the control circuit is configured to control the peripheral circuits to set a bit line voltage in the program verifying operation to have a higher level than a bit line voltage in the read operation, and a bit line voltage in the erase verifying operation to have a lower level than the bit line voltage in the read operation.
申请公布号 US9218887(B2) 申请公布日期 2015.12.22
申请号 US201414186665 申请日期 2014.02.21
申请人 SK HYNIX INC. 发明人 Jung Sung Wook
分类号 G11C16/24;G11C16/34;G11C16/04 主分类号 G11C16/24
代理机构 Hauptman Ham, LLP 代理人 Hauptman Ham, LLP
主权项 1. A semiconductor memory device, comprising: a memory cell array configured to store data; peripheral circuits configured to perform a program verifying operation, a read operation, and an erase verifying operation on the memory cell array; and a control circuit configured to control the peripheral circuits, wherein the peripheral circuits are configured to apply a first bit line voltage to bit lines when a read voltage is applied to a word line of selected memory cells in the read operation, apply a second bit line voltage to the bit lines when a first verifying voltage is applied to the word line in the program verifying operation, and apply a third bit line voltage to the bit lines when a second verifying voltage is applied to the word line in the erase verifying operation, wherein the second bit line voltage is higher than the first bit line voltage and the third bit line voltage is lower than the first bit line voltage, wherein the second bit line voltage is set to have a higher level than the first bit line voltage based on retention characteristics of the memory cells in the semiconductor memory device, and the third bit line voltage is set to have a lower level than the first bit line voltage based on disturb characteristics of the memory cells in the semiconductor memory device.
地址 Icheon-Si, Gyeonggi-Do KR