发明名称 Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout
摘要 A method comprises generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions comprises a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the spacing values.
申请公布号 US9218448(B2) 申请公布日期 2015.12.22
申请号 US201414158968 申请日期 2014.01.20
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 Ho Chia-Ming;Chen C. Y.;Hsueh Hsiu-Wen;Huang Jun-Fu;Chou Shao-Heng
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Hauptman Ham, LLP 代理人 Hauptman Ham, LLP
主权项 1. A method comprising: generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit, each of the plurality of multiple patterning decompositions comprising: a first pattern associated with a first mask;a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set;a width value associated with at least one of the first pattern or the second pattern; anda spacing value between the first pattern and the second pattern; and generating a file comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions, the plurality of dielectric constant values being based on the width values and the spacing values associated with the plurality of multiple patterning decompositions, wherein generating the file comprises: simulating, for at least some of the plurality of multiple patterning decompositions, a worst-case performance value yielding the plurality of dielectric constant values for the at least some of the plurality of multiple patterning decompositions; andpopulating the file with the worst-case performance value.
地址 TW