发明名称 Inferred base layer block for TEXTURE<sub>—</sub>BL mode in HEVC based single loop scalable video coding
摘要 An apparatus for coding video data using a single-loop decoding approach may include a memory unit and a processor in communication with the memory unit. In an example, the memory unit stores the video data, the video data including a base layer and an enhancement layer. The base layer includes a base layer block, a non-constrained INTRA mode block, and an INTER mode block. The base layer block includes a sub-block located at least partially within one of the non-constrained INTRA mode block or the INTER mode block. The enhancement layer includes an enhancement layer block located at a position in the enhancement layer corresponding to a position of the base layer block in the base layer. The processor approximates pixel values of the sub-block and determines, based at least in part on the approximated pixel values, pixel values of the enhancement layer block.
申请公布号 US9219913(B2) 申请公布日期 2015.12.22
申请号 US201313914387 申请日期 2013.06.10
申请人 QUALCOMM Incorporated 发明人 Tu Chengjie;Wang Xianglin;Chen Jianle;Guo Liwei;Karczewicz Marta
分类号 H04N7/26;H04N19/39;H04N19/105;H04N19/30;H04N19/187;H04N19/44 主分类号 H04N7/26
代理机构 Knobbe, Martens, Olson & Bear, LLP 代理人 Knobbe, Martens, Olson & Bear, LLP
主权项 1. An apparatus configured to code video data using a single-loop decoding approach, the apparatus comprising: a memory unit configured to store the video data, wherein the video data comprises a base layer and an enhancement layer, wherein the base layer comprises a base layer block in a first frame, a first block in the first frame, and a second block in the first frame, wherein the first block is predicted based on pixels neighboring the first block, wherein the pixels neighboring the first block are reconstructed based on a third block in a second frame different from the first frame, and wherein the second block is predicted based on a fourth block in a third frame different from the first frame and the second frame; and a processor in communication with the memory unit, the processor configured to: generate a predictor for the base layer block based on one or more first pixel values in the enhancement layer;approximate a reconstruction of the base layer block by approximating pixel values of the base layer block based on the predictor for the base layer block and a prediction residual for the base layer block, wherein the base layer block is located at least partially within a portion of the first block and a portion of the second block; anddetermine, based at least in part on the approximated pixel values of the base layer block, second pixel values of an enhancement layer block in the first frame in the enhancement layer, wherein the enhancement layer block is located at a position in the enhancement layer corresponding to a position of the base layer block in the base layer.
地址 San Diego CA US