Multiple data rate memory with read timing information

摘要

A memory includes a memory array, read circuitry, and a strobe generator. The read circuitry is configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock. The strobe generator is configured to provide a strobe signal with the read data, wherein the strobe generator provides the strobe signal in accordance with a second clock. The second clock is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees.

主权项

1. A memory controller for interfacing with a memory, comprising:
address/control terminals, the address/control terminals configured to address the memory to request read data from the memory; clock terminals, the clock terminals configured to provide true and complementary data clocks to the memory to request the read data be provided between coincident edges of the true and complementary clocks; phase terminals, the phase terminals configured to provide true and complementary phase clocks to the memory that are out of phase with the true and complementary data clocks to aid the memory in generating a strobe signal; and data terminals, the data terminals configured to receive the read data requested from the memory for sensing; and a strobe terminal, the strobe terminal configured to clock the sensing in response to the strobe signal from the memory.