| 摘要 |
PROBLEM TO BE SOLVED: To suppress excessive estimation of clock jitter.SOLUTION: Regarding a clock path, correlation R between a noise application timing at which an electric power source noise signal is applied, and path delay of the clock path at the time when the electric power source noise signal is applied is acquired. Further, to the clock path, set is a noise application timing width W based on a clock signal input from a front step of circuit. With the acquired correlation R, difference D of path delay in the set noise application timing width W is calculated, and the maximum value of the difference D is estimated as a clock jitter of the clock path. The clock to be estimated is more reduced than a worst value, and excessive estimation is suppressed. |
