WAFER STRESS CONTROL WITH BACKSIDE PATTERNING

摘要

Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication.

主权项

1. A method of forming a semiconductor structure, comprising:
depositing a pad layer to a front side and a back side of a semiconductor substrate; forming a plurality of back side deep trenches on the back side of the semiconductor substrate to form a back side deep trench pattern; recessing the plurality of back side deep trenches; removing the pad layer from the back side of the semiconductor substrate; depositing a polysilicon layer on the back side of the semiconductor substrate and covering the plurality of back side deep trenches; and forming a plurality of front side deep trenches on the front side of the semiconductor substrate to form a front side deep trench pattern, wherein the front side deep trench pattern is a minor of the back side deep trench pattern.