Memory Controller with Processor for Generating Interface Adjustment Signals

摘要

Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.

主权项

1. A memory controller, comprising:
an interface for coupling the memory controller to one or more dynamic random access memory devices, the interface including plurality of interface control circuits, each for controlling a sampling timing offset for sampling data received on a respective signal path between the memory controller and a respective memory device of the one or more dynamic random access memory devices and a transmit timing offset for transmitting data to the respective memory device; a processor to execute machine-readable instructions to calibrate the plurality of interface control circuits, wherein the processor comprises circuitry configured to execute said machine-readable instructions; and memory to store the machine-readable instructions for execution by the processor, and the machine-readable instructions are for executing a process to determine at least one timing adjustment signal for each interface control circuit of the plurality the interface control circuits.