COUNTER WITH OVERFLOW FIFO AND A METHOD THEREOF

摘要

Embodiments of the present invention relate to an architecture that extends counter life by provisioning each counter for an average case and handles overflow via an overflow FIFO and an interrupt to a process monitoring the counters. This architecture addresses a general optimization problem, which can be stated as, given N counters, for a certain CPU read interval T, of how to minimize the number of storage bits needed to store and operate these N counters. Equivalently, this general optimization problem can also be stated as, given N counters and a certain amount of storage bits, of how to optimize and increase CPU read interval T. This architecture extends the counter CPU read interval linearly with depth of the overflow FIFO.

主权项

1. A counter architecture implemented in a network device, the counter architecture comprises:
N wrap-around counters, wherein each of the N wrap-around counters is associated with a counter identification; and an overflow FIFO used and shared by the N wrap-around counters, wherein the overflow FIFO stores the associated counter identifications of all counters that are overflowing.