| 发明名称 |
TRANSLATION LAYER FOR CONTROLLING BUS ACCESS |
| 摘要 |
A translation layer includes a plurality of first buffers and a controller to assert one or more ready signals corresponding to one or more of the plurality of first buffers in response to the one or more of the plurality of first buffers being less than full. The one or more of the plurality of first buffers receives data or control information from one or more corresponding components in response to the ready signal being asserted concurrently with one or more valid signals asserted by the one or more corresponding components. |
| 申请公布号 |
US2015363166(A1) |
申请公布日期 |
2015.12.17 |
| 申请号 |
US201414304191 |
申请日期 |
2014.06.13 |
| 申请人 |
ATI Technologies ULC |
发明人 |
Christidis Kostantinos D. |
| 分类号 |
G06F5/14;G06F13/362;G06F13/16;G06F5/06 |
主分类号 |
G06F5/14 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a plurality of first buffers; and a controller to assert at least one ready signal corresponding to at least one of the plurality of first buffers in response to the at least one of the plurality of first buffers being less than full, wherein the at least one of the plurality of first buffers receives data or control information from at least one corresponding component in response to the ready signal being asserted concurrently with at least one valid signal asserted by the at least one corresponding component. |
| 地址 |
East Markham CA |
