HOLD-TIME OPTIMIZATION CIRCUIT AND RECEIVER WITH THE SAME

摘要

A hold-time optimization circuit includes a correction circuit and a delay control circuit. The delay control circuit delays a clock signal for a delay time so as to generate a delay clock signal. The correction circuit generates a correction pulse signal according to transition edges of a data signal and transition edges of the delay clock signal. The delay time of the delay control circuit is optimized according to the correction pulse signal. The data signal is sampled according to the delay clock signal.

主权项

1. A hold-time optimization circuit, comprising:
a delay control circuit, delaying a clock signal for a delay time so as to generate a delay clock signal, wherein the delay time is adjusted according to a correction pulse signal; and a correction circuit, generating the correction pulse signal according to transition edges of a data signal and transition edges of the delay clock signal, wherein the data signal is sampled according to the delay clock signal.