ARRAY FANOUT PASS TRANSISTOR STRUCTURE

摘要

A device, such as an integrated circuit including memory, includes an array of memory cells on a substrate. A row/column line, such as a local word line or local bit line, is disposed in the array. The row/column line includes a pass transistor structure comprising a semiconductor strip in a first patterned layer over the substrate. The semiconductor strip includes a semiconductor channel body, a contact region on one side of the semiconductor channel body, and an extension on another side of the semiconductor channel body, which reaches into the memory cells in the array. A select line in a second patterned layer crossing the semiconductor channel body is provided. The pass transistor structure can be implemented in a fanout structure for row/column lines in the array.

主权项

1. A device comprising:
a substrate; an array of memory cells on the substrate, including a row/column line; the row/column line including a pass transistor structure comprising a semiconductor strip in a first patterned layer over the substrate, the semiconductor strip including a semiconductor channel body, a contact region on one side of the semiconductor channel body, and an extension on another side of the semiconductor channel body, the extension coupled to memory cells in the array; a select line in a second patterned layer crossing the semiconductor channel body; a row/column line select signal generator which produces a select signal, connected to the select line; and a row/column line voltage generator which produces a row/column line voltage, connected to the contact region.