HARDWARE PROTECTION OF INLINE CRYPTOGRAPHIC PROCESSOR

摘要

A real time, on-the-fly data encryption system is shown operable to encrypt and decrypt the data flow between a secure processor and an unsecure external memory system. Multiple memory segments are supported, each with it's own separate encryption capability, or no encryption at all. Data integrity is ensured by hardware protection from code attempting to access data across memory segment boundaries. Protection is also provided against dictionary attacks by monitoring multiple access attempts to the same memory location.

主权项

1. A data encryption system comprising:
a plurality of encryption cores operable to perform a variety of encryption, decryption or message authentication functions, an external memory interface operable to receive encrypted data from said encryption cores and to write the encrypted data to an external memory, and further operable to receive encrypted data from said external memory and provide it to the encryption cores, an external memory comprising of one or more memory segments, connected to said external memory interface.