AFLL WITH INCREASED TIMING MARGIN

摘要

In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency. The integrated circuit includes a voltage regulator that provides a power-supply voltage to the second DCO. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage. Furthermore, the AFLL adjusts a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage. In this way, an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced.

主权项

1. An integrated circuit, comprising a first sub-frequency-locked loop in an asymmetric frequency-locked loop (AFLL) that provides a clock signal, wherein the first sub-frequency-locked loop includes:
a first digitally controlled oscillator (DCO) configured to output a first signal having a first fundamental frequency; a second DCO configured to output a second signal having a second fundamental frequency; a voltage regulator that provides a power-supply voltage to the second DCO; and control logic, electrically coupled to the first DCO and the second DCO, configured to select one of the first DCO and the second DCO based on an instantaneous value of the power-supply voltage and an average power-supply voltage, wherein the AFLL is configured to modify a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage.