LSI DESIGN METHOD

摘要

Buffers on a clock tree are reduced, as long as there is enough set-up margin, in order to reduce power consumption in the clock tree. An FF group coupled to a partial tree, which is a part of the clock tree and expanded from the branch point being focused on, is defined as the target FF and the other FFs are defined as non-target FFs. The target buffer of an elimination candidate and the target and non-target FFs are defined so as not to change the slack in principle in a signal propagation path between the non-target FFs even if the buffer is eliminated. The buffer which can be eliminated is specified within a range in each signal propagation path which has a start point at the non-target FF and an end point at the target FF and in each signal propagation path between the target FFs.

主权项

1. An LSI design method for a clock tree including a plurality of buffers between a clock generation source and a plurality of timing definition circuits, the LSI design method comprising:
using a computer to perform the steps of:
defining one or more target buffers which exists between one branch point in the clock tree and a next branch point in one branch extending from the one branch point toward the timing definition circuits,defining the timing definition circuits, which are coupled to terminals of a partial clock tree expanding from the one branch, as target timing definition circuits,defining the timing definition circuits except the target timing definition circuits as non-target timing definition circuits,defining a set-up margin in at least one signal propagation path having a start point at one of the non-target timing definition circuits and an endpoint at one of the target timing definition circuits,performing a timing analysis, andeliminating one or more of the target buffers which reduces the set-up margin based on a result of the timing analysis, while maintaining set up margins to be greater than or equal to zero in all the signal propagation paths having a start point at one of the non-target timing definition circuits and an endpoint at one of the target timing definition circuits.