SOLID-STATE IMAGE SENSING DEVICE HAVING SIGNAL HOLDING CIRCUITS FOR HOLDING IMAGE DIGITAL SIGNALS CONVERTED BY ANALOG-DIGITAL CONVERTERS

摘要

A solid-state image sensing device according to the invention which can reduce an instantaneous current occurring in transferring image digital signals from analog-digital converters to registers to reduce noise sneaking into the analog-digital converters and a pixel array includes a pixel array, a vertical scanning circuit, a plurality of column ADCs, a plurality of registers, and control signal generation units. The control signal generation units are provided for respective groups into which the column ADCs and the registers disposed on one side of the pixel array are divided, and generate control signals of different timings, for respective units including at least one group, of transfer of converted image digital signals to the registers from the column ADCs operating in parallel.

主权项

1. A solid-state image sensing device comprising:
a pixel array having a plurality of imaging elements arranged in a matrix; a row selection circuit for selecting a row in the pixel array; a plurality of analog-digital converters which are disposed in respective columns in the pixel array and convert image analog signals read out from imaging elements selected by the row selection circuit into image digital signals; a plurality of signal holding circuits for holding the image digital signals converted by the analog-digital converters in respective columns in the pixel array; and control signal generation units for generating control signals for controlling timings of transfer of the converted image digital signals from the analog-digital converters to the signal holding circuits, wherein the plurality of the analog-digital converters and the plurality of the holding circuits are divided into a plurality of groups, wherein the plurality of groups include a first, a second and a third group, wherein the control signal generation units include a first, a second and a third logic circuits, each of the first, the second, the third logic circuits respectively selects the first, the second and the third groups by generating the control signals by performing logic operations on the transfer signals and a selection signal, wherein the selection signal is inputted to the second logic circuit via a first delay circuit and inputted to the third logic circuits via the first delay circuit and a second delay circuit.