System and Method for a Pulse Generator

摘要

According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input.

主权项

1. A method of generating a clock pulse, the method comprising:
receiving a leading edge of an input clock at a clock input at a time when an enable signal is active; generating a leading edge of an output clock at a clock output based on the received leading edge of the input clock; latching a logic value corresponding to the leading edge of the output clock at the clock output; after the logic value is latched, preventing changes at the clock input from affecting the latched logic value; resetting the latched logic value after a first delay time thereby causing a falling edge at the clock output; and maintaining the reset logic value until a second leading edge is received at the clock input.