发明名称 半導体回路のバスシステム
摘要 An exemplary semiconductor circuit bus system includes: a first bus comprised of distributed buses and having a first transfer rate; a second bus with a second transfer rate higher than the first transfer rate; a transmission node; a bus interface (IF) to connect the transmission node to the first bus; a router which connects the first and second buses; and a reception node connected to the second bus. The bus IF controls the flow rate of data flowing through the transmission routes of the first bus by reference to information about the amounts of transmissible data of the transmission routes. The router allocates the amounts of transmissible data to the transmission routes of the first bus and provides information about the amounts of transmissible data of the transmission routes for the bus IF and also controls the flow rate of the data flowing through the second bus.
申请公布号 JP5834178(B2) 申请公布日期 2015.12.16
申请号 JP20140527396 申请日期 2013.10.31
申请人 パナソニックIPマネジメント株式会社 发明人 山口 孝雄;吉田 篤;石井 友規;得津 覚
分类号 H04L12/40;H04L12/701;H04L12/911 主分类号 H04L12/40
代理机构 代理人
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