| 摘要 |
A cache 2 can receive addresses from two channels in parallel. The cache has two tag memories. The main tag memory 10 contains tags for all entries in the cache. A micro-tag array 22 is smaller than the main tag array and holds a proper subset of its entries. If two addresses are received simultaneously, one is looked up in the main tag array and the other is looked up in the micro-tag array. If a miss is detected in the micro-tag array, then the address may be looked up in the main tag array. A tag may be stored in the micro-tag array in the event of a miss in the main tag array. The read latency of the micro-tag array may be lower than that of the main tag array by at least a clock cycle. |
