发明名称 CLOCK FREQUENCY CONTROLLER
摘要 <p><P>PROBLEM TO BE SOLVED: To solve the problem that, although a maximum clock frequency is determined so that the processing of a sound processing circuit processing a frame is not collapsed, from an analysis of header storing information on the frame, a clock with an excessive frequency is supplied because the processing may be completed early depending on the content of main data. <P>SOLUTION: The clock is supplied to a signal processing circuit processing an input data signal at a frequency lower than a maximum frequency determined by a frequency decision circuit, and the clock is varied according to the processing status of one frame by a frequency determination circuit, thereby reducing power consumption. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2009004002(A) 申请公布日期 2009.01.08
申请号 JP20070162088 申请日期 2007.06.20
申请人 PANASONIC CORP 发明人 TAKAMATSU TAKAKO;MUROYAMA TAKASHI
分类号 G11B20/10;G06F1/04 主分类号 G11B20/10
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