发明名称 POWER CONSUMPTION ANALYSIS DEVICE AND POWER CONSUMPTION ANALYSIS METHOD
摘要 PROBLEM TO BE SOLVED: To provide a power consumption analysis device capable of performing power consumption analysis in a gate level with high level of accuracy by operation simulation of RTL (Register Transfer Level) data. SOLUTION: This power consumption analysis device has an RTL supply part 1, an RTL analysis part 2, a net list generation part 3, an RTL/net list comparison part 4, a form verification information supply part 5, a mapping file generation part 6, a monitor signal generation part 7, a test bench description generation part 8, a test data supply part 9, an RTL simulation part 10, a monitor part 11, and a power consumption analysis part 12. The RTL data and a net list are compared, description related to a clock gating cell not present in the RTL data but present in the net list is added to the RTL data, the RTL simulation is performed based on the RTL data after the addition, a duty ratio or a toggle rate of an input/output signal of each of various kinds of the clock gating cells is detected, and power consumption of the various kinds of the clock gating cells is analyzed, so that power consumption of a circuit including the clock gating cell can be easily analyzed with high level of accuracy. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009003618(A) 申请公布日期 2009.01.08
申请号 JP20070162510 申请日期 2007.06.20
申请人 TOSHIBA CORP 发明人 KAWABE NAOYUKI
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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