| 摘要 |
This invention discloses a tap circuit in a summer of a decision feedback equalizer (DFE), the tap circuit comprises a differential pair of received signal lines, a current source having a magnitude being substantially proportional to a tap weight coupled between a first node and a ground, a plurality of NMOS transistors controllably coupled the current source to either one of the received signal lines, and DFE data signals and DEF logic sign signals being coupled only to the gates of the plurality of NMOS transistors, wherein tap circuit can operate at low supply voltage without losing speed.
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