DELAY LOCK LOOP FOR REDUCING A STATIC PHASE OFFSET AND METHOD OF THE SAME

摘要

PURPOSE: A delay locked loop and a control method thereof are provided to synchronizing an output clock of the delay locked loop with a reference input clock by reducing a static phase error due to a charge pump current mismatch. CONSTITUTION: A differential transducer(100) generates a differential clock and a differential reverse clock. A voltage control delay unit(200) generates a first multi phase clock group including (N+1) multi phase clocks based on the 0-th reference multiple clock extracted from the differential clock. A harmonic lock prevention block(300) changes four multiple phase clock to the force control signal. A phase detector(400) transmits an up signal and a down signal to a charge pump(500). The charge pump generates the control voltage matched with the up signal and the down signal. A lock detector(600) grasps the normal locking of the delay locked loop. An auxiliary charge pump(700) generates an inner up control voltage and an inner down control voltage.