发明名称 |
PROCESSING ARCHITECTURES WITH TYPED INSTRUCTION SETS |
摘要 |
An architecture for microprocessors, in which instructions include a type identifier, selects one of several interpretation registers. The interpretation registers hold information for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of expanded instructions. Preferably the type identifiers also distinguish sequencer instructions from processing-element instructions, and can even distinguish among different types of sequencer instructions (as well as among different types of processing-element instructions). |
申请公布号 |
EP2082325(A4) |
申请公布日期 |
2009.11.25 |
申请号 |
EP20070843324 |
申请日期 |
2007.09.27 |
申请人 |
3DLABS INC., LTD. |
发明人 |
BLOOMFIELD, JONATHAN;ROBSON, JOHN, DAVID;MURPHY, NICHOLAS, J.N. |
分类号 |
G06F9/30;G06F9/318;G06F15/00 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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