| 摘要 |
A method for forming a wiring of a semiconductor device using a dual damascene is provided to distribute polishing stress by rounding an upper edge of a trench through a wet etching process. A first interlayer insulating film(12) is deposited in a front side of a semiconductor substrate(10). A lower wiring(14) is formed in an upper side of the first interlayer insulating film. A second interlayer insulating film(16) is deposited in the upper part of the lower wiring. An etch stop layer(18) is formed by a chemical vapor deposition process. A third interlayer insulating film(20) is deposited in the upper part of the semiconductor substrate by performing a chemical vapor deposition process. A trench(24) is formed by etching the third interlayer insulating film. An upper edge(26) of the trench is rounded by performing an isotropic etching process.
|
