| 摘要 |
PROBLEM TO BE SOLVED: To provide a multiprocessor system that increase efficiency of data transfer between a plurality of processors. SOLUTION: In a configuration having, for example, a microcomputer [1]MC1 and a system memory MEM1 thereof, and a microcomputer [2]MC2 and a system memory MEM2 thereof, a data relay device PCIC is disposed on a path of data transfer from MEM1 to MEM2. PCIC includes a first buffer BFA and a second buffer BFB, which are accessed alternately when large volume data is transferred. For example, when a DMA controller DMAC1 in MC1 stores data into BFB, a DMA controller DMAC2 in MC2 reads out data from BFA (S63), and then DMAC1 stores the subsequent data into BFA emptied (S64). COPYRIGHT: (C)2009,JPO&INPIT
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