IMPLEMENTATION OF ADDER COMPARE SELECT BLOCK OF VITERBI DECODER FOR HIGH DATA RATE TRANSMISSION

摘要

An ACS(Adder compare selector) and a method thereof are provided to offer a high data transmission rate to a low frequency clock by connecting the ACS of the viterbi decoder serially. A first operation unit(401) adds a part of values inputted from a BMC(Branch Metric Calculator) and a existing path metric value stored in an SM(state metric memory). A second operation unit(402) has the same structure as the first operation unit and adds the remainder among the result value of the first operation unit and the value inputted from the BMC. A comparison unit selects a survival path with the minimum path after accumulating the output value of the second operation unit and outputs the selected path to a TBM(Trace Back Memory).