发明名称 |
METHOD AND/OR APPARATUS FOR IMPLEMENTING REDUCED BANDWIDTH HIGH PERFORMANCE VC1 INTENSITY COMPENSATION |
摘要 |
<p>An apparatus comprising a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate an output signal and one or more motion vectors in response to (i) a bitstream signal and (ii) a predictor signal. The second circuit may be configured to generate one or more reference data pixels in response to an address signal and the output signal. The third circuit may be configured to generate the predictor signal and address signal in response to (i) the motion vectors and (ii) the reference data pixels.</p> |
申请公布号 |
EP2070194(A2) |
申请公布日期 |
2009.06.17 |
申请号 |
EP20070838427 |
申请日期 |
2007.09.17 |
申请人 |
LSI CORPORATION |
发明人 |
PEARSON, ERIC;JOCH, PETER |
分类号 |
H03M7/00;H04N7/26;H04N7/36;H04N7/50 |
主分类号 |
H03M7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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