发明名称 Tamper-resistant processing method
摘要 <p>The subject of the disclosed technology is, when a crypto-processing is performed utilizing an information processing device buried in an IC card, etc., to decrease the relationship between the waveform of the consumption current and the contents of the crypto-processing as a countermeasure against a tamper which observes the waveform of a consumption current. A solution means is shown in the following. When a decryption processing of an RSA cryptogram is performed according to CRT, in step 608, for every unit bit block of XP a modular exponentiation calculation is performed, and the partial result of CP up to the calculated bit block is stored in a memory. In step 609, for every unit bit block of XQ a modular exponentiation calculation is performed and the partial result of CQ up to the calculated bit block is stored in a memory. In step 606, a random number is generated, and in step 607, it is decided that step 608 is to be executed or step 609 is to be executed corresponding to the value of the random number.</p>
申请公布号 EP1239365(B1) 申请公布日期 2009.06.17
申请号 EP20010119739 申请日期 2001.08.27
申请人 HITACHI, LTD. 发明人 KAMINAGA, MASAHIRO;ENDO, TAKASHI;WATANABE, TAKASHI;OHKI, MASARU
分类号 G06F12/14;G07C5/08;B60K6/08;G06F7/72;G06F9/302;G06F9/318;G06F21/06;G06F21/24;G06K19/073;G09C1/00;H04L9/10 主分类号 G06F12/14
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