Lateral semiconductor device

摘要

MOS transistor having a high source-drain breakdown BVds, a low on resistance and a high electric current driving capacity. On resistance is lowered by forming an N well layer (25) for lowering on resistance in the drift region. The N well layer (25) is disposed beneath the gate electrode (5) and away from the N well layer (26) with a certain space between them. This space ensures the withstand voltage at the edge of the gate electrode (5) of the drain layer (11) side. Also, the N well layer (26) is formed on the surface of an epitaxial layer (2) in the region that includes a P+L layer. The edge of the N well layer (26) of the drain layer side (11) is located near the edge of the P+L layer (13) of the drain layer side and away from the N well layer (25). This space makes the expansion of depletion layer from the P+L layer (13) easier, further improving the withstand voltage.