| 摘要 |
PROBLEM TO BE SOLVED: To provide a technique for reducing the cost of a semiconductor device for logic on which nonvolatile memories are mixedly mounted by reducing the plane size of a capacitance element for a power supply circuit. SOLUTION: A first capacitance portion is formed between: an active region ACT of a semiconductor substrate, which is provided via an insulating film in the same layer with the gate insulating film of an nMIS for selection or the gate insulating film of one of field-effect transistors of a peripheral circuit; and a lower electrode CGcb formed of a conductor film being the same layer with the gate electrode of the nMIS for selection. A second capacitance portion is formed between: a lower electrode CGcb provided via an insulating film of a multilayer structure including a charge storage layer; and an upper electrode MGct formed of a conductor film being the same layer with the gate electrode of an nMIS for memory. The first capacitance portion and second capacitance portion are connected in parallel to constitute a laminated capacitance element C1, and grooves 1a for a plurality of capacitance elements is formed in the active region ACT of the semiconductor substrate below the lower electrode CGcb. COPYRIGHT: (C)2009,JPO&INPIT
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