发明名称 PARALLEL ANALOG/DIGITAL CONVERSION CIRCUIT, SAMPLING CIRCUIT, AND COMPARING AMPLIFIER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a sampling circuit, a comparing amplifier circuit and a parallel analog/digital conversion circuit which can achieve a low consumption power and a small area by reducing a number of amplifiers. SOLUTION: The sampling circuit includes: an amplifier A1 which amplifies input signal; a switch SW2 for resetting input to the amplifier A1; multiple capacitors C1, C2 whose one side terminals are connected to an output of the amplifier A1; and multiple switches SW3, SW4 for sampling which are connected to other side terminals of the capacitors C1, C2, respectively. After the switch SW2 for resetting the input and the switch SW3 for sampling are made shorted for a given length of time, respectively, the switch SW4 is made shorted for a given length of time. Thus signals Vo21, Vo22 based on input signals are alternately output from the other side terminals of the respective capacitors C1, C2. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009089347(A) 申请公布日期 2009.04.23
申请号 JP20080023398 申请日期 2008.02.02
申请人 SONY CORP 发明人 SHIMIZU YASUHIDE;MURAYAMA SHIGEMITSU;KUDO KOHEI;YATSUDA HIROTOMO
分类号 H03M1/36 主分类号 H03M1/36
代理机构 代理人
主权项
地址