| 摘要 |
A first memory cell array includes a first bit line and a second bit line arranged to read data out of a memory cell containing a ferroelectric capacitor. A second memory cell array includes a third bit line and a fourth bit line arranged to read data out of a memory cell containing a ferroelectric capacitor. A sense amp circuit detects and amplifies a potential difference caused between any two of the first through fourth bit lines. A decoupling circuit selectively connects any two of the first through fourth bit lines to the sense amp circuit and decouples the remainder from the sense amp circuit. A bit-line potential control circuit is arranged between the decoupling circuit and the first and second memory cell arrays to fix the bit lines decoupled from the sense amp circuit by the decoupling circuit to a first potential.
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