| 摘要 |
On the first hierarchical layer, the input image adjuster selects an overlap processing area from a frequency-unconverted image. On the first hierarchical layer, the overlap processor performs overlap processing on the overlap processing area, and holds the image data of the remaining processing areas, which cannot be frequency-converted. The remaining processing area, which is a linear area, can have an image width reduced down to the displacement between the overlap processing area and the block areas. The processes on the second hierarchical layer are identical to those on the first hierarchical layer. As a result, the encoder maximizes the advantage of the high performance achieved by hardware implementation.
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