| 摘要 |
Variable delay circuit constructed by connecting plural unit circuits in series which can change a delay time from input of signal until output of the signal by increasing or decreasing the number of unit circuits through which the signal concerned is passed. Each of the unit circuits is operable in a through operation mode in which a signal input from a unit circuit at the front stage is output to a unit circuit at the rear stage and also a signal input from a unit circuit at the rear stage is output to a unit circuit at the front stage and a feedback operation mode in which a signal input from a unit circuit at the front stage to a unit circuit at the front stage and a signal input from a unit circuit at the rear stage is output to a unit circuit at the rear stage.
|
