| 摘要 |
A semiconductor memory device of a stack structure is provided to reduce a loading of a column selection signal and to increase a data processing speed by arranging a column decoder array between two banks. A semiconductor memory device of a stack structure includes a first bank(BA-U), a second bank(BA-D), and a column decoder array(10). The second bank is separated from the first bank. The column decoder array is positioned between the first bank and the second bank. A cell of the first bank and a cell of the second bank are selected by the same column selection signal at the same time. The column decoder array provides the column selection signal to the first bank and the second bank at the same time. The column selection signal is used in order to select the cells of the first bank and the second bank by decoding a column address.
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