| 摘要 |
PROBLEM TO BE SOLVED: To provide a DMA controller for transferring data by distributing a plurality of channels. SOLUTION: In a DMA controller 4, an arbiter part 11 selects a data transfer request from channels ch0 to ch2 to which image processing units 3R, 3G and 3B are connected, based on a prescribed transfer sequence, and temporarily stores packet data from the selected channels ch0 to ch2 in one of packet buffers 14a and 14b, and a unit control part 12 transfers the information of the channels ch0 to ch2 as the transfer source of the stored packet data and the transfer request to a system bus interface part 15, and the system bus interface part 15 creates a memory address corresponding to the channels ch0 to ch2 based on the register information of the channels ch0 to ch2 of a transfer register part 16, and transfers the packet data of the packet buffers 14a and 14b through a system bus 5 to a memory 6. COPYRIGHT: (C)2009,JPO&INPIT
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