| 摘要 |
A memory controller with multiple delayed timing signals. Control information is provided by a first output driver circuit to a first signal path. Write data, associated with the control information, is provided by a second output driver circuit to a second signal path. Timing information is provided by a third output driver to a third signal path. Rising and falling edge transitions of the timing information indicate times at which subsequent symbols of the write data are valid on the signal path. The timing information is delayed with respect to the control information to account for a difference between a time that the control information takes to reach the destination device while traversing the first signal path and a time that the write data takes to reach the destination device while traversing the second signal path.
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