发明名称 DOUBLE CHANNEL MATCHING CIRCUIT
摘要 <p>Connection topology of input terminals (2), elements (4a, 4b, 4c, 4d) and a load (5) is made as a "7-segment display" applied to numerical display for a calculator or a digital clock and the like. That is, if the uppermost and lowermost segments among three horizontally extending segments in the 7-segment display are assigned to the input terminals (2) and the load (5) is assigned to one remaining horizontally extending segment, four remaining longitudinal segments correspond to the elements (4a, 4b, 4c, 4d). The elements (4a, 4b, 4c, 4d) are an inductor having inductance of 4.030nH, an inductor having inductance of 11.208nH, an inductor having inductance of 2.497nH, and a capacitor having capacitance of 2.233pF, respectively. This circuitry can reduce the total number of elements to 4 thereby realizing low loss property. In addition, as a resonance circuit is eliminated from constituent circuits and a scale of a ladder circuit is reduced, highly stable impedance matching is attained against impedance fluctuation of the load (5).</p>
申请公布号 WO2009028199(A1) 申请公布日期 2009.03.05
申请号 WO2008JP02351 申请日期 2008.08.28
申请人 PANASONIC CORPORATION;SANGAWA, USHIO 发明人 SANGAWA, USHIO
分类号 H03H7/38;H04B1/04 主分类号 H03H7/38
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